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Mt8196/v0.1 #11205

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3908be7
drivers: mediatek: use cache line size for AFE buffer alignment
May 28, 2026
ee61509
mt8196: update ADSP system memory address
Sep 15, 2026
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2 changes: 1 addition & 1 deletion src/drivers/mediatek/afe/afe-memif.c
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Original file line number Diff line number Diff line change
Expand Up @@ -437,7 +437,7 @@ static int memif_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
*value = 4;
break;
case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
*value = 16;
*value = DCACHE_LINE_SIZE;
break;
case DMA_ATTR_BUFFER_PERIOD_COUNT:
*value = 4;
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2 changes: 1 addition & 1 deletion src/platform/mt8196/include/platform/lib/memory.h
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Expand Up @@ -24,7 +24,7 @@
#define VECTOR_SIZE 0x700
#define SRAM_START (SRAM_BASE + VECTOR_SIZE)

#define DRAM_BASE 0x90000000
#define DRAM_BASE 0x92200000
#define DRAM0_SIZE 0x500000
#define MAILBOX_BASE (DRAM_BASE + DRAM0_SIZE)
#define DSP_SYS_SIZE 0xA00000
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7 changes: 3 additions & 4 deletions src/platform/mt8196/platform.c
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Expand Up @@ -141,9 +141,9 @@ const struct xthal_MPU_entry __xt_mpu_init_table[] __section(".ResetVector.text"
XTHAL_MPU_ENTRY(0x1a110000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_DEVICE), // audio
XTHAL_MPU_ENTRY(0x4e100000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // sram
XTHAL_MPU_ENTRY(0x4e180000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE), // unused
XTHAL_MPU_ENTRY(0x90000000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // dram
XTHAL_MPU_ENTRY(0x90500000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE), // dram
XTHAL_MPU_ENTRY(0x90900000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE), // unused
XTHAL_MPU_ENTRY(0x92200000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_WRITEBACK), // dram
XTHAL_MPU_ENTRY(0x92700000, 1, XTHAL_AR_RWXrwx, XTHAL_MEM_NON_CACHEABLE), // dram
XTHAL_MPU_ENTRY(0x92b00000, 1, XTHAL_AR_NONE, XTHAL_MEM_DEVICE), // unused
};

const unsigned int __xt_mpu_init_table_size __section(".ResetVector.text") =
Expand Down Expand Up @@ -214,4 +214,3 @@ void platform_wait_for_interrupt(int level)
{
arch_wait_for_interrupt(level);
}

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