[rtl] Keep dummy instructions out of single step, minstret and the Zcmp expander

dv/cosim/spike_cosim.cc

@@ -217,6 +217,10 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
   // (If the current step causes a synchronous trap, it will be
   //  recorded against the current pc)
   initial_spike_pc = (processor->get_state()->pc & 0xffffffff);
+  // Debug-mode state the instruction executes in; a trap on a stepped
+  // instruction enters debug mode within this same step, but the cpuctrlsts
+  // flag update is decided by the mode at trap take.
+  bool initial_spike_debug_mode = processor->get_state()->debug_mode;
   processor->step(1);
 
   // ISS
@@ -277,7 +281,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
         return false;
       }
 
-      handle_cpuctrl_exception_entry();
+      handle_cpuctrl_exception_entry(initial_spike_debug_mode);
 
       // This is all the checking possible when consider a
       // synchronously-trapping instruction that never retired.
@@ -533,8 +537,8 @@ void SpikeCosim::leave_nmi_mode() {
 #endif
 }
 
-void SpikeCosim::handle_cpuctrl_exception_entry() {
-  if (!processor->get_state()->debug_mode) {
+void SpikeCosim::handle_cpuctrl_exception_entry(bool debug_mode_at_trap) {
+  if (!debug_mode_at_trap) {
     bool old_sync_exc_seen = change_cpuctrlsts_sync_exc_seen(true);
     if (old_sync_exc_seen) {
       set_cpuctrlsts_double_fault_seen();

dv/cosim/spike_cosim.h

@@ -88,7 +88,7 @@ class SpikeCosim : public simif_t, public Cosim {
 
   bool change_cpuctrlsts_sync_exc_seen(bool flag);
   void set_cpuctrlsts_double_fault_seen();
-  void handle_cpuctrl_exception_entry();
+  void handle_cpuctrl_exception_entry(bool debug_mode_at_trap);
 
   void initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec,
                           uint32_t mhpm_counter_num);

dv/uvm/core_ibex/directed_tests/directed_testlist.yaml

@@ -77,6 +77,35 @@
   test_srcs: mcounteren_test/mcounteren_lock_test.S
   config: riscv-tests
 
+- test: dummy_instr_minstret_test
+  desc: >
+    Dummy instructions must not be counted in minstret. The retired-instruction
+    count over a straight-line block of known length is read with dummy
+    instruction insertion disabled, enabled at its highest rate, and disabled
+    again; the cosim compares the read values as well.
+  iterations: 1
+  test_srcs: dummy_instr_test/dummy_instr_minstret_test.S
+  config: riscv-tests
+  rtl_params:
+    PMPEnable: 1
+    SecureIbex: 1
+
+- test: dummy_instr_zcmp_test
+  desc: >
+    Dummy instructions must not disturb an expanded Zcmp sequence. cm.push,
+    cm.pop, cm.mvsa01, cm.mva01s, cm.popret and cm.popretz are executed
+    repeatedly with dummy instruction insertion at its highest rate and every
+    architectural effect is checked. Cosim mismatches are non-fatal because
+    the cosim does not enable Zcmp for the reference model.
+  iterations: 1
+  test_srcs: dummy_instr_test/dummy_instr_zcmp_test.S
+  config: riscv-tests
+  rtl_params:
+    PMPEnable: 1
+    SecureIbex: 1
+    RV32ZC: ["ibex_pkg::RV32ZcaZcmp", "ibex_pkg::RV32ZcaZcbZcmp"]
+  sim_opts: +disable_cosim=1
+
 - test: pmp_mseccfg_test_rlb1_l0_0_u0
   desc: >
     mseccfg test
@@ -475,18 +504,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/scall.S
   config: riscv-tests
 
-- test: shamt
+- test: sh-misaligned
   desc: >
-    riscv test - shamt
+    riscv test - sh-misaligned
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/shamt.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sh-misaligned.S
   config: riscv-tests
 
-- test: sh-misaligned
+- test: shamt
   desc: >
-    riscv test - sh-misaligned
+    riscv test - shamt
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/sh-misaligned.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32mi/shamt.S
   config: riscv-tests
 
 - test: sw-misaligned
@@ -524,6 +553,13 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/divu.S
   config: riscv-tests
 
+- test: mul
+  desc: >
+    riscv test - mul
+  iterations: 1
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mul.S
+  config: riscv-tests
+
 - test: mulh
   desc: >
     riscv test - mulh
@@ -545,13 +581,6 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mulhu.S
   config: riscv-tests
 
-- test: mul
-  desc: >
-    riscv test - mul
-  iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/mul.S
-  config: riscv-tests
-
 - test: rem
   desc: >
     riscv test - rem
@@ -566,25 +595,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32um/remu.S
   config: riscv-tests
 
-- test: addi
-  desc: >
-    riscv test - addi
-  iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/addi.S
-  config: riscv-tests
-
 - test: add
   desc: >
     riscv test - add
   iterations: 1
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/add.S
   config: riscv-tests
 
-- test: andi
+- test: addi
   desc: >
-    riscv test - andi
+    riscv test - addi
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/andi.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/addi.S
   config: riscv-tests
 
 - test: and
@@ -594,6 +616,13 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/and.S
   config: riscv-tests
 
+- test: andi
+  desc: >
+    riscv test - andi
+  iterations: 1
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/andi.S
+  config: riscv-tests
+
 - test: auipc
   desc: >
     riscv test - auipc
@@ -650,18 +679,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/fence_i.S
   config: riscv-tests
 
-- test: jalr
+- test: jal
   desc: >
-    riscv test - jalr
+    riscv test - jal
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jalr.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jal.S
   config: riscv-tests
 
-- test: jal
+- test: jalr
   desc: >
-    riscv test - jal
+    riscv test - jalr
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jal.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/jalr.S
   config: riscv-tests
 
 - test: lb
@@ -706,18 +735,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/lw.S
   config: riscv-tests
 
-- test: ori
+- test: or
   desc: >
-    riscv test - ori
+    riscv test - or
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/ori.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/or.S
   config: riscv-tests
 
-- test: or
+- test: ori
   desc: >
-    riscv test - or
+    riscv test - ori
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/or.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/ori.S
   config: riscv-tests
 
 - test: sb
@@ -741,18 +770,25 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/simple.S
   config: riscv-tests
 
+- test: sll
+  desc: >
+    riscv test - sll
+  iterations: 1
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sll.S
+  config: riscv-tests
+
 - test: slli
   desc: >
     riscv test - slli
   iterations: 1
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slli.S
   config: riscv-tests
 
-- test: sll
+- test: slt
   desc: >
-    riscv test - sll
+    riscv test - slt
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sll.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slt.S
   config: riscv-tests
 
 - test: slti
@@ -769,18 +805,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltiu.S
   config: riscv-tests
 
-- test: slt
+- test: sltu
   desc: >
-    riscv test - slt
+    riscv test - sltu
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/slt.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltu.S
   config: riscv-tests
 
-- test: sltu
+- test: sra
   desc: >
-    riscv test - sltu
+    riscv test - sra
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sltu.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sra.S
   config: riscv-tests
 
 - test: srai
@@ -790,11 +826,11 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srai.S
   config: riscv-tests
 
-- test: sra
+- test: srl
   desc: >
-    riscv test - sra
+    riscv test - srl
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sra.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srl.S
   config: riscv-tests
 
 - test: srli
@@ -804,13 +840,6 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srli.S
   config: riscv-tests
 
-- test: srl
-  desc: >
-    riscv test - srl
-  iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/srl.S
-  config: riscv-tests
-
 - test: sub
   desc: >
     riscv test - sub
@@ -825,18 +854,18 @@
   test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/sw.S
   config: riscv-tests
 
-- test: xori
+- test: xor
   desc: >
-    riscv test - xori
+    riscv test - xor
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xori.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xor.S
   config: riscv-tests
 
-- test: xor
+- test: xori
   desc: >
-    riscv test - xor
+    riscv test - xori
   iterations: 1
-  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xor.S
+  test_srcs: ../../../../vendor/riscv-tests/isa/rv32ui/xori.S
   config: riscv-tests
 
 # Test-suite: riscv-arch-tests

dv/uvm/core_ibex/directed_tests/dummy_instr_test/dummy_instr_minstret_test.S

@@ -0,0 +1,66 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Dummy instructions must not be counted in minstret.
+#
+# The retired-instruction count over a straight-line block of known length is
+# read before, during and after dummy instruction insertion is enabled at its
+# highest rate (cpuctrlsts.dummy_instr_en = 1, dummy_instr_mask = 0, which
+# inserts a dummy at least every four instructions). Each window spans the
+# first csrr and eight nops, so the two reads must always differ by nine.
+# The cosim compares the read values against the reference model as well.
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+# cpuctrlsts (0x7c0): bit 2 dummy_instr_en, bits 5:3 dummy_instr_mask.
+#define CPUCTRLSTS 0x7c0
+#define CPUCTRLSTS_DUMMY_INSTR_EN 0x4
+
+.macro CHECK_MINSTRET_DELTA idx
+  li   gp, \idx
+  csrr t0, minstret
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  nop
+  csrr t1, minstret
+  sub  t2, t1, t0
+  li   t3, 9
+  bne  t2, t3, fail
+.endm
+
+RVTEST_RV32M
+RVTEST_CODE_BEGIN
+
+  # Baseline with dummy instructions disabled.
+  CHECK_MINSTRET_DELTA 1
+
+  # Enable dummy instruction insertion at the highest rate and repeat the
+  # measurement; the insertion points walk across the window.
+  csrsi CPUCTRLSTS, CPUCTRLSTS_DUMMY_INSTR_EN
+  li   t4, 32
+1:
+  CHECK_MINSTRET_DELTA 2
+  addi t4, t4, -1
+  bnez t4, 1b
+
+  # Disable again and re-check the baseline.
+  csrci CPUCTRLSTS, CPUCTRLSTS_DUMMY_INSTR_EN
+  CHECK_MINSTRET_DELTA 3
+
+  j    pass
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+  TEST_DATA
+RVTEST_DATA_END