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1. sv-pipelined-cpu-uvm sv-pipelined-cpu-uvm Public

   Custom 16-bit 3-stage pipelined CPU in SystemVerilog with UVM verification, RAW hazard handling, assertions, constrained-random testing, and functional coverage.

   SystemVerilog 1

2. DIY-WAV-Player-w-ESP32 DIY-WAV-Player-w-ESP32 Public

   As my first embedded project, I tried to build a basic WAV player using an MCU, SD Card module, LCD Screen, DAC module, and Input buttons.

   C++ 6

3. PONG-with-FPGA-and-ESP32 PONG-with-FPGA-and-ESP32 Public

   For my ECE3700 final project at the U of U, we made a playable PONG with FPGA, two input buttons, and ESP32. We chose to display the score on the screen as "HP bars".

   Verilog 1

4. cpp-study cpp-study Public

   Self-studying c++, archiving my activities

   C++ 1